About GreenCenter
The power consumption of the current data centers (e.g. for web servers) is one of the most challenging issues in the current IT ecosystem. In 2002, the global data centre footprint, including equipment use and embodied carbon, was 76 MtCO2e and this is expected to more than triple by 2020 to 259 MtCO2e – making it the fastest-growing contributor to the ICT sector’s carbon footprint, at 7% in relative terms. The percentage of the CO2 emission from the data centers is expected to grow up to 18% of the total ICT emissions, therefore several consortium tries to find ways to reduce significantly the energy consumption (e.g. the GreenTouch initiative is targeting a 1000x reduction in the total ICT sector by 2020). Meeting this challenge is prohibitive without a dramatic improvement in energy efficiency, decreasing the computation and communication energy consumption per bit. Therefore, more energy efficient processors, storage elements, switches and memories are required that will provide increased processing power with reduced energy consumption. Currently, almost all of the web servers are based on high performance x86 architectures but are not power optimized. A possible alternative that is recently investigated, mainly by the research community and start-up companies, is the use of processors that are currently targeting embedded devices (e.g ARM). These processors have been designed for low power consumption devices thus if they are used properly, they can lower significantly the power consumption of the data centers.
In this project we will investigate how to design efficient hardware accelerators that will augment Multi-processors Systems-on-a-Chip (MPSoC) based on embedded processors that can be deployed in data centers that require low power consumption (e.g. MicroServers). We will investigate how to accelerate several tasks for data centers (e.g. web server application such as XML parsing and memory management) by augmenting these processors with the right hardware acceleration units in order to reduce the power consumption and increase the processing power. These hardware accelerators can be used either as coprocessors (hosted into FPGAs with hardcore processors) or as an Intellectual Property core (IP core) that will be embedded into future MPSoC systems. In the case of FPGAs, we will also investigate how the dynamic reconfiguration can be applied to virtualized web servers. Based on the web server’s application requirements the FPGA will be reconfigured to meet the processing demands by loading the appropriate hardware accelerator. In addition we will investigate the use of more energy-efficient architectures for the packet switches (e.g. commodity Ethernet switches) used in the data center networks. Finally, we will prototype the design in a MPSoC that will consists of several low power hard-cores processors and FPGA-based hardware accelerators and we will evaluate the proposed scheme in terms of performance and power consumption.
Overall the main targets of this project will be the followings:
In this project we will investigate how to design efficient hardware accelerators that will augment Multi-processors Systems-on-a-Chip (MPSoC) based on embedded processors that can be deployed in data centers that require low power consumption (e.g. MicroServers). We will investigate how to accelerate several tasks for data centers (e.g. web server application such as XML parsing and memory management) by augmenting these processors with the right hardware acceleration units in order to reduce the power consumption and increase the processing power. These hardware accelerators can be used either as coprocessors (hosted into FPGAs with hardcore processors) or as an Intellectual Property core (IP core) that will be embedded into future MPSoC systems. In the case of FPGAs, we will also investigate how the dynamic reconfiguration can be applied to virtualized web servers. Based on the web server’s application requirements the FPGA will be reconfigured to meet the processing demands by loading the appropriate hardware accelerator. In addition we will investigate the use of more energy-efficient architectures for the packet switches (e.g. commodity Ethernet switches) used in the data center networks. Finally, we will prototype the design in a MPSoC that will consists of several low power hard-cores processors and FPGA-based hardware accelerators and we will evaluate the proposed scheme in terms of performance and power consumption.
Overall the main targets of this project will be the followings:
- Study and analysis of the most computational intensive tasks in the current cloud-based data centers applications
- Design and implementation of hardware acceleration units for the most common applications in web servers (e.g. XML parsing, memory management, compression, encryption) in order to augment current processors and reduce the power consumption.
- Development of interfaces that will allow the fast communication and integration with embedded processors (e.g. advanced switches for communication with low power hard-core processors) and the use of advanced optical networks for intra-rack and inter-rack communication in the data centers
- The hardware accelerators units will be either hosted into future FPGA with hard-core processors or will be available as IP cores that can be incorporated into future Multi-Processor chips (e.g. for MicroServers).