On October 9, 2014, we organized a Thematic Session on EU projects focused on Microservers at the Computing Systems Week of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) in Athens, Greece.
11:00-11:10 Introduction, Dr. Christoforos Kachris
11:10-11:30 Nanostreams: On the Viability of Micro-servers for Real-time Data Analytics,
Prof. Dimitris Nikolopoulos, Queen's University of Belfast
11:30-11:50 Mont-Blanc: High Performance Computing based on mobile embedded processors,
Dr. Alejandro Rico, BSC
11:50:12:10 Euroserver: Fast, Energy-Efficient Microserver Communication in the EuroServer Project,
Dr. Iakovos Mavroidis, FORTH
12:10-12:30 GreenCenter: A MapReduce Accelerator for multi-core all-programmable FPGAs,
Prof. Georgios Sirakoulis, DUTH
11:10 On the Viability of Micro-servers for Real-time Data Analytics
Abstract: Datacenters that host real-time analytical workloads incur extremely high operational costs in order to meet performance and latency requirements of their hosted applications. Recently, ARM-based microservers have emerged as a viable alternative to high-end servers, promising scalable performance via scale-out approaches and low energy consumption. In this talk we explore the viability of ARM-based microservers for real-time analytical processing in financial market workloads. We compare an ARM-based microserver against a state-of-the-art x86 server. We define new energy and performance metrics to compare those platforms in the context of datacenters for real-time analytics and give insight on the particular requirements of financial workloads. Our findings suggest that under an iso-power scenario microservers can reduce energy costs by up to 70% while meeting workload-specific QoS criteria, despite having a significant peak performance disadvantage again heavyweight servers.
11:30 High Performance Computing based on mobile embedded processors
Abstract: In view of the experiences within the Mont-Blanc project at the Barcelona Supercomputing Center, this talk will describe possibilities, results and challenges raised when developing high-performance computing platforms from low cost and energy efficient mobile processors and commodity components.
11:50 Fast, Energy-Efficient Microserver Communication in the EuroServer Project
Abstract: Data centers need to cope with the ever-increasing demand for storing and processing of data, and need to do so within fixed power consumption limitations. The EuroServer FP7 project is developing energy-efficient microservers for such data centers, using new technologies, such as silicon on insulator (SOI) and 3D stacking, in order to integrate a large number of lightweight computing nodes into the shared infrastructure of power, cooling fans, and I/O devices in a common chassis. The UNIMEM architecture, introduced by John Goodacre in EuroServer, brings compute and memory components closer together, using a fast and low-power communication layer among the compute nodes. After briefly describing the above, this talk will focus on our implementation of UNIMEM, a distributed global address space communication infrastructure among multiple coherence islands (multiple symmetric multiprocessors), which provides an efficient mechanism for remote memory borrowing, local memory sharing and RDMA operations. Moreover, this talk will describe a virtualized 10GigEthernet NIC that is shared among multiple virtual machines running on multiple coherence islands.
12:10 A MapReduce Accelerator based on all-programmable FPGAs
Abstract: The main aim of the GreenCenter project is to develop a novel configurable hardware accelerator that is used to speed up the processing of multi-core and cloud computing applications based on the MapReduce programming framework. The proposed MapReduce configurable accelerator is augmented to multi-core processors and it performs a fast indexing and accumulation of the key/value pairs based on an efficient memory architecture. This accelerator is used to alleviate the processors from executing the Reduce tasks, and thus executing only the Map tasks and emitting the intermediate key/value pairs to the hardware acceleration unit that performs the Reduce operation. The MapReduce accelerator has been implemented to a multi-core FPGA with embedded ARM processors (Xilinx Zynq FPGA) and has been integrated with the MapReduce programming framework under Linux. The performance evaluation shows that the proposed accelerator can achieve up to 1.8x system speedup of the MapReduce applications and hence reduce significantly the execution time of multi-core and cloud computing applications.